Analysis of DAC performance metrics (SFDR, SNR, INL, DNL, GE, RB)
Transistor mismatch, clock jitter, process variation
Analog and DSP modeling
Efficient
and Fast Simulation of Electronic Circuits and Systems via Spectral Method.
The project goal of the project is development of prototype simulator of RF circuits, which utilizes spectral algorithms developed at the University of Arizona. The algorithms employ Chebyshev polynomial series for rapid and very accurate solution of circuit equations. Preliminary simulator, SPEC, based on the new algorithm is substantially more efficient and more accurate than other simulators designed. The algorithm is inherently parallel and thus it is suitable for implementation in parallel computing systems. Distributed elements (for example interconnections – transmission lines) are handled very easily and naturally in SPEC.
The
SPEC can be used in design of RF power amplifiers, where it can assist in
determination of stability regions. Stability is a significant problem in
design. For example current design of RF power amplifier requires approximately
2 weeks, but its stabilization requires 6 months as it involves high level of
bench experiments caused by lack of adequate simulation support. Another
important area of application of SPEC is investigation of phase stability in
oscillators, which is very critical in high-speed digital circuits, RF circuits
(local oscillators), and mixed-signal circuits. In mixed-signal signal circuits
such as signal converters phase noise of oscillator determines clock jitter,
which in turn effects significantly converter performance.
Mixed signal simulator, PAMIX, was designed for MS Windows operating system.
This simulator, originally developed for analysis of Digital-to-Analog Converters (DAC) used in wireless communication hardware, utilizes novel technique, which is called Perfect Sampling Technique (PST). The PST was developed at the University of Arizona. The behavioral modeling of circuitry and PST give superior performance and accuracy of solutions over traditional simulators utilizing Fast Fourier Transform (FFT) based methods. The PAMIX is intended to help engineers in VLSI as well as system level design involving high performance DAC’s and other mixed-signal circuits.
Issues addressed
|
Analysis of DAC performance metrics (SFDR, SNR, INL, DNL, GE, RB) |
|
Transistor mismatch, clock jitter, process variation |
|
Analog and DSP modeling |
This project is dedicated to development of dynamically re-configurable mixed-signal circuits constructed using the novel technology of Field Programmable Analog Arrays (FPAA) combined with existing well-established technology of Field Programmable Gate Arrays (FPGA). The FPAA can be utilized to enrich educational laboratories by providing a platform for experiments in control engineering, analog signal filtering, and switched capacitor circuit design. The Motorola developed FPAA package includes an excellent PC based software support system for application design. Additional hardware requirements are minimal as FPAA is almost a self contained, stand-alone system. A FPAA can be used to build filters for analog signals as well as other kinds of analog applications. The initial work concentrated on adaptive filtering with dynamic reconfiguration based on 2 parallel FPAA chips cooperating with a digital control system. Theoretical studies and measurements of transition behavior of the switching process between the 2 FPAA chips and analysis of limitations imposed by hardware imperfections were performed and are described in publications. The experimental system is an excellent vehicle to learn about intricacies in performance of mixed-signal circuits and is used for verification of theoretical predictions as well as for model modifications.
Mixed-Signal Development Board (MSDB) was designed for rapid prototyping of mixed-signal circuits. The board utilizes Field Programmable Analog Arrays, microprocessor, and Field Programmable Gate Arrays to achieve full analog and digital programmability. The board is controlled by the 65C02 microcontroller built in the development board supplied by the Western Design Center. The accompanying Project Manager for MS windows software package provides flexible programming for board components.
Issues addressed:
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Digital and analog programmable devices (FPAA, FPGA) |
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Rapid prototyping |
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Hardware design |
An idea of Virtual Laboratory (VL) is based on assumption that measurement equipment placed in one particular location can be accessed at other locations using remote control and data exchange through communication networks. VL can be extended to connect many separately located measurement set-ups into one virtual system. Such a system would constitute Virtual Distributed Measurement System (VDMS), which would allow complex experiments without gathering all necessary instruments in one place.
Issues addressed:
|
Distributed and remotely controlled systems |
|
Measurement equipment |
|
Network protocols/communication |
The project entitled Signal Integrity in circuits and systems (SI) involves investigation of simulation techniques supporting signal integrity analysis in digital, RF , and mixed-signal circuits. This includes definitions of suitable performance metrics, modeling of circuit imperfections, the effects of imperfections on circuit performance, and multi-criteria optimization techniques.
The Laboratory offers short courses for practicing engineers. Some elements of (SI) are included in regular courses (ECE570, ECE554, ECE654). Important investigations are also carried under the project “SPEC based estimation of phase noise in oscillators”.
Oscillators are very widely employed in many functions, for example setting timing in digital and mixed-signal circuits. They are also used in other important functions such as local oscillators in transceivers. Increasing speed of circuits imposes stricter requirements on timing, which results in demand for improved stability of oscillators. Portable communication equipment imposes additional constraints on timing and oscillator performance. Restrictions on frequency spectra in communication systems also result in tight requirements concerning stability of oscillator circuits.
Oscillator instabilities influence performance of other system components and eventually that of entire system. For example timing jitter limits the maximum clock frequency in digital systems. In signal conversion timing jitter limits the dynamic range of DAC’s or effective number of bits in ADC’s. In mixers noisy local oscillator may increase interference with adjacent channels. The stability of oscillators is particularly critical in CMOS technology, which is very popular, inexpensive, but it is also inherently noisy. This project deals with analytical methods and SPEC simulation techniques in analysis and design of oscillators for low phase noise.
This project deals with behavioral modeling of converters for wireless communication. We constructed the mathematical model for computation of effective number of bits in ideal data converters as a function of clock jitter, signal frequency, and sampling phase. We have established a first-order model for clock jitter as a function of cross-coupling capacitances and aggressor signal variations, power and ground fluctuations, and signal rise times as determined by selected technology parameters. The model incorporates the substrate coupling effects. A model for Spur-Free Dynamic Range (SFDR) as a function of current source output impedance and transistor mismatch has also been developed.
We developed behavioral modeling for Digital-to-Analog Converter (DAC) based on the concept of current steering and implemented in CMOS technology. The modeling captures such circuit imperfections as transistor mismatch, clock jitter due to the substrate coupling, non-simultaneous switching, and finite output impedance of current sources. To support the analysis and design a specialized program, PAMIX, was developed. The DAC’s segmentation of current sources into binary and thermometer code was optimized using the methodology of Multi-Criteria Optimization (MCO). The performance metrics such as SFDR, Glitch Energy, Differential Non-Linearity error were considered. The effects of imperfections and correlation between the quantization error, sampling and input signal frequencies can be depicted using the program PAMIX.
A
suitable program for optimal segmentation of current sources with the use of
modeling and MCO techniques was developed and applied to optimize the
segmentation of a specific design of 14-bit DAC.
The project Multi-Criteria Optimization (MCO) of circuits and systems involves investigation of optimization methodologies and application in design of packages, mixed-signal circuits, and microelectronic systems.
The
MCO was applied to optimization of digital-to-analog converter (DAC) based on
current steering techniques with segmentation of current sources into binary and
thermometer coding. In the segmented digital-to-analog DAC’s, the digital
decoding circuits are fabricated on the same chip as the analog circuits.
Therefore coupling between noisy digital circuits and sensitive analog circuits
via the substrate is significant. A model of substrate coupling capturing the
effects of coupling on clock jitter and Spur Free Dynamic Range (SFDR) was
developed. This comprehensive approach includes the current noise signatures of
logic blocks and noise transport model for the substrate. The performance
metrics are computed using the program PAMIX.
The performance
metrics such as SFDR, Glitch Energy, Differential Non-Linearity error are in
conflict with each other and the use of MCO methodology is necessary.
Packaging considerations in system design come into play when there is a need to: (1) partition the system into chips, (2) decide about chip packaging, (3) decide about technology for second or higher level packaging. Several factors such as cost of packaging, electrical performance, reliability, mechanical performance etc. have to be taken into account in the decision process. These factors are in conflict with each other. For example improvement of the electrical performance (as expressed by the speed of the system operation) is achieved by miniaturization of packaging, which yields shorter signal transmission paths and consequently shorter delays. However, this improvement is accompanied by the increase of dissipated power density caused by two effects: a) the faster circuit dissipates more power and b) the dissipation takes place in a smaller structure. The increased power density will cause the system components to either operate at higher temperature, which will reduce their reliability, or it will require better cooling which in turn will increase the system cost. Here MCO techniques and suitable software support were very effective in finding the optimal solution.