// adder.v
// 4-bit Structural and Behavior Adder Implemenatations

// ------------------------------------------------------------------
// Copyright (c) 2006 Susan Lysecky, University of Arizona
// Permission to copy is granted provided that this header remains
// intact. This software is provided with no warranties.
// ------------------------------------------------------------------
`timescale 1ns / 1ps


// 1-bit full adder
module FA(a, b, ci, co, s);
   input a, b, ci;
   output co, s;
   wire t1, t2, t3;

   and and_1(t1, a, b);
   and and_2(t2, a, ci);
   and and_3(t3, b, ci);
   or or_1(co, t1, t2, t3);
   xor(s, a, b, ci);
	
endmodule


// 4-bit adder, structural ripple carry implementation
module Adder_Struct(A, B, Result);
   input [3:0] A, B;
   output [3:0] Result;
   wire t_c1, t_c2, t_c3, t_c4; // intermediate carry values
   
   FA FA_1(A[0], B[0], 1'b0, t_c1, Result[0]);
   FA FA_2(A[1], B[1], t_c1, t_c2, Result[1]);
   FA FA_3(A[2], B[2], t_c2, t_c3, Result[2]);
   FA FA_4(A[3], B[3], t_c3, t_c4, Result[3]);
endmodule


// 4-bit adder behavioral implementation 
module Adder_Beh(A, B, Result);

   input [3:0] A;
   input [3:0] B;
   output reg[3:0] Result;

   always @ (A or B)
   begin 
      Result <= A + B;
   end

endmodule