// top_circuit_tb.v

// ------------------------------------------------------------------
// Copyright (c) 2007 Susan Lysecky, University of Arizona
// Permission to copy is granted provided that this header remains
// intact. This software is provided with no warranties.
// ------------------------------------------------------------------

`timescale 1ns / 1ns

module Top_Circuit_tb;
     reg clk_t, rst_t, start_t;
	  reg [7:0] val_t;
	  reg [6:0] start_addr_t, end_addr_t;
     wire [7:0] num_value_t;

     Top_Circuit TOP1(clk_t, rst_t, val_t, start_t, start_addr_t, end_addr_t, num_value_t);	  

     always begin
          clk_t <= 0;
          #25;
          clk_t <= 1;
          #25;
     end

     initial begin
          rst_t <= 1;
          start_t <= 0;
          start_addr_t <= 7'd0;
          end_addr_t <= 7'd64;
          val_t <= 8'h05;
          #65;
          rst_t <= 0;
          #50;

          start_t <= 1;
          #100;
          start_t <= 0;

          #15000;
     end
endmodule