// mem.v

// ------------------------------------------------------------------
// Copyright (c) 2007 Susan Lysecky, University of Arizona
// Permission to copy is granted provided that this header remains
// intact. This software is provided with no warranties.
// ------------------------------------------------------------------

`timescale 1ns / 1ns


module mem(clk, en, rw, addr, data);
     input clk, en, rw;
     input [5:0] addr;
     inout [7:0] data;

     reg data_en = 0;
     reg [7:0] data_val;

     parameter MemSize = 64;
     parameter MemWidth = 8;

     // delcare memory
     reg [MemWidth-1:0] MemoryA [0:MemSize-1];

     // setup databus
     assign data = data_en ? data_val : 8'bzzzzzzzz;
	  
     // initialize contents of memory from input file
     initial
     begin
          $readmemh("MemA.txt", MemoryA);
     end

     // memory write functionality (synchronous)	  
     always @(posedge clk)
     begin
          if( en == 1 && rw == 0 ) begin
               MemoryA[addr] <= data;
          end
     end

     // memory read functionality (asynchronous)
     always @*
     begin
          if( en == 1 && rw == 1 ) begin
               data_en <= 1;
               data_val <= MemoryA[addr];
          end
          else begin
               data_en <= 0;
               data_val <= 8'b00000000;
          end
     end									  
endmodule