Hardware/Software Partitioning of Floating-Point Applications
While hardware/software partitioning has been shown to provide significant performance gains, most hardware/software partitioning approaches are limited to partitioning computational kernels utilizing integers or fixed point implementations. Software developers often initially develop an application using built-in floating point representations and later convert the application to a fixed point representation – a potentially time consuming process. We are currently developing a hardware/software partitioning approach for floating point applications that eliminates the need for developers to rewrite software applications for fixed point implementations. Instead, the proposed approach incorporates efficient, configurable floating point to fixed point and fixed point to floating point hardware converters at the boundary between the hardware coprocessors and memory. This effectively separates the system into a floating point domain consisting of the microprocessor and memory subsystem and a fixed point computing domain consisting of the partitioned hardware coprocessors, thereby providing an efficient and rapid method for implementing fixed point hardware coprocessors. Our hardware/software partitioning approach for a floating point application provides application speedups of 4.3X on average without requiring any designer effort to re-implement software with a fixed point representation.
Publications
- L. Saldanha, R. Lysecky. Hardware/Software Partitioning of Floating Point Software Applications to Fixed-Point Coprocessor Circuits. International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), 2008.
Received Best Paper Award