Just-in-Time FPGA Compilation

Just-in-Time (JIT) FPGA Compilation

Just-in-time (JIT) FPGA compilation takes a netlist in a standard netlist binary format, and execute technology mapping, placement, and routing. We have developed a JIT compiler consisting of lean versions of technology mapping, placement, and routing algorithms that require an order of magnitude less execution time and memory requirements compared with their desktop-based counterparts while producing acceptable quality hardware circuits.

Publications

1. R. Lysecky, F. Vahid, S. Tan. A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2005.
2. R. Lysecky, F. Vahid, S. Tan. Dynamic FPGA Routing for Just-in-Time Compilation. IEEE/ACM Design Automation Conference (DAC), June 2004.
3. R. Lysecky, F. Vahid. A Codesigned On-Chip Logic Minimizer. IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2003.
4. R. Lysecky, F. Vahid. On-Chip Logic Minimization. IEEE/ACM 40th Design Automation Conference (DAC), June 2003.