Warp Processors

Warp Processors

Warp processors dynamically and transparently optimize an executing software binary by moving software kernels to on-chip configurable logic, improving performance by 7.4X and reducing energy consumption by 49% on average. Extensive research has shown that hardware/software partitioning, the process of dividing an application between software executing on a microprocessor and hardware co-processors, can result in overall software speedups as well as reducing system energy. By developing a custom CAD-oriented field programmable gate array (FPGA) and lean on-chip decompilation, partitioning, and just-in-time (JIT) FPGA compilation tools, warp processors provide the performance and energy benefits of HW/SW partitioning without any designer effort, expertise, or knowledge. Using warp processors, a designer can use any programming language and compiler to create a truly portable application binary. With future extensions and enhancements to warp processor, a warp processor will determine how to best execute the portable binary either as software executing on a processor, entirely in hardware using configurable logic, or partitioning the application between software and hardware.

Low Power Warp Processing

Our original warp processor design was primarily performance-driven and did not focus on power consumption, which is becoming an increasingly important design constraint. Alternatively, a low-power warp processor leverages the dynamic partitioning benefits of warp processors and the power saving benefits ofvoltage and frequency scaling to create a high-performance embedded architecture capable of dynamically reducing power consumption without degrading performance. By focusing on reducing power consumption, our low-power design achieves an average power reduction of 74%.

Publications

1. R. Lysecky, F. Vahid. Design and Implementation of a MicroBlaze-based Warp Processor. ACM Transactions on Embedded Computing Systems (TECS), To Appear.
2. R. Lysecky. Scalability and Parallel Execution of Warp Processing - Dynamic Hardware/Software Partitioning. International Journal on Parallel Programming, To Appear.
3. F. Vahid, G. Stitt, R. Lysecky. Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. IEEE Computer, Vol. 41, No. 7, pp. 40-46, July 2008.
4. R. Lysecky, G. Stitt, F. Vahid. Warp Processors. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, No. 3, pp. 659 - 681, 2006.
5. R. Lysecky. Low-Power Warp Processor for Power Efficient High-Performance Embedded Systems. IEEE/ACM Design Automation and Test in Europe Conference (DATE), 2007.
6. R. Lysecky, F. Vahid. A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. IEEE/ACM Design Automation and Test in Europe Conference (DATE), March 2005.
7. R. Lysecky, F. Vahid. A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. IEEE/ACM Design Automation and Test in Europe Conference (DATE), February 2004.
8. G. Stitt, R. Lysecky, F. Vahid. Dynamic Hardware/Software Partitioning: A First Approach. IEEE/ACM 40th Design Automation Conference (DAC), June 2003.

Patents

1. F. Vahid, R. Lysecky, G. Stitt. Warp Processor for Dynamic Hardware/Software Partitioning. US Patent Pending, 2004.