Roman Lysecky, Assistant Professor CV
Department of Electrical and Computer Engineering
University of Arizona
Tucson, AZ 85721
Office: ECE 356F, 520-621-6192, Fax: 520-621-3862
rlysecky@ece.arizona.edu

Research Interests

Embedded system design, with emphasis on dynamic adaptability, HW/SW partitioning, soft processor cores, real-time systems, and low power FPGAs. Current research efforts include real-time dynamically adaptable embedded systems, software-defined soft-multicore SOC design, and dynamically adaptable soft processor cores. I am currently looking for motivated, energetic Ph.D. students interested in embedded systems for several research projects involving FPGAs.

Current Research Projects

Low-Power Warp Processing

Real-time Hardware/Software Partitioning

Low-Power FPGAs

Application-Specific FPGAs

Warp Processors

Warp processors dynamically and transparently optimize an executing software binary by moving software kernels to on-chip configurable logic, improving performance by 7.4X and reducing energy consumption by 49% on average. Extensive research has shown that hardware/software partitioning, the process of dividing an application between software executing on a microprocessor and hardware co-processors, can result in overall software speedups as well as reducing system energy. By developing a custom CAD-oriented field programmable gate array (FPGA) and lean on-chip decompilation, partitioning, and just-in-time (JIT) FPGA compilation tools, warp processors provide the performance and energy benefits of HW/SW partitioning without any designer effort, expertise, or knowledge. Using warp processors, a designer can use any programming language and compiler to create a truly portable application binary. With future extensions and enhancements to warp processor, a warp processor will determine how to best execute the portable binary either as software executing on a processor, entirely in hardware using configurable logic, or partitioning the application between software and hardware.

Just-in-Time (JIT) FPGA Compilation

Just-in-time (JIT) FPGA compilation takes a netlist in a standard netlist binary format, and execute technology mapping, placement, and routing. We have developed a JIT compiler consisting of lean versions of technology mapping, placement, and routing algorithms that require an order of magnitude less execution time and memory requirements compared with their desktop-based counterparts while producing acceptable quality hardware circuits.