Publications

Patents

1. F. Vahid, R. Lysecky, G. Stitt. Warp Processor for Dynamic Hardware/Software Partitioning. US Patent 7,356,672, 2008.

Books

1. F. Vahid, R. Lysecky. VHDL for Digital Design. John Wiley and Sons, 2007.
2. F. Vahid, R. Lysecky. Verilog for Digital Design. John Wiley and Sons, 2007.

Journal Publications

1. J. Mu, R. Lysecky. Autonomous Hardware/Software Partitioning and Voltage/Frequency Scaling for Low-Power Embedded Systems. ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 1-19, To Appear.
2. R. Kalra, R. Lysecky. Configuration Locking and Schedulability Evaluation for Reduced Reconfiguration Overheads of Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), pp. 1-4, To Appear.
3. L. Saldanha, R. Lysecky. Float-to-Fixed and Fixed-to-Float Hardware Converters for Rapid Hardware/Software Partitioning of Floating Point Software Applications to Static and Dynamic Fixed Point Coprocessors. Journal on Design Automation of Embedded Systems, Vol. 13, No. 3, pp. 139-157, 2009.
4. R. Lysecky, F. Vahid. Design and Implementation of a MicroBlaze-based Warp Processor. ACM Transactions on Embedded Computing Systems (TECS), Vol. 8, No. 3, Article 22, pp. 1-22, 2009.
5. R. Lysecky. Scalability and Parallel Execution of Warp Processing - Dynamic Hardware/Software Partitioning. International Journal on Parallel Programming, Vol. 36, No.5, pp. 478-492, October 2008.
6. F. Vahid, G. Stitt, R. Lysecky. Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. IEEE Computer, Vol. 41, No. 7, pp. 40-46, July 2008.
7. R. Lysecky, G. Stitt, F. Vahid. Warp Processors. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, No. 3, pp. 659 - 681, 2006.
8. C. Zhang, F. Vahid, R. Lysecky. A Self-Tuning Cache Architecture for Embedded Systems. ACM Transactions on Embedded Computing Systems (TECS), Vol. 3, No. 2, pp. 407-425, May 2004.
9. R. Lysecky, S. Cotterell, F. Vahid. A Fast On-Chip Profiler Memory using a Pipelined Binary Tree. IEEE Transaction on Very Large Scale Integration (TVLSI), Vol. 12, No. 1, pp. 120-122, January 2004.
10. F. Vahid, R. Lysecky, C. Zhang, G. Stitt. Highly Configurable Platforms for Embedded Computing Systems. Microelectronics Journal, Vol. 34, No. 11, pp. 1025-1029, 2003.
11. R. Lysecky, F. Vahid. Pre-fetching for Improved Bus Wrapper Performance in Cores. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 7, Number 1, pp. 58-90, January 2002.

Conference Publications

1. K. Shankar, R. Lysecky. Non-Intrusive Dynamic Application Profiling for Multitasked Applications. Design Automation Conference (DAC), pp. 130-135, 2009.
   
2. L. Saldanha, R. Lysecky. Hardware/Software Partitioning of Floating Point Software Applications to Fixed-Point Coprocessor Circuits. International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), pp. 49-54, 2008.
   Received Best Paper Award
3. A. Nair, R. Lysecky. Non-Intrusive Dynamic Application Profiler for Detailed Loop Execution Characterization. International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), pp. 23-30, 2008.
4. M. Hammerquist, R. Lysecky. Design Space Exploration for Application-Specific FPGAs in System-on-a-Chip Designs. IEEE International SOC Conference (SOCC), pp. 279-282, 2008.
5. R. Lysecky. Low-Power Warp Processor for Power Efficient High-Performance Embedded Systems. IEEE/ACM Design Automation and Test in Europe Conference (DATE), pp. 141-146, 2007.
6. D. Sheldon, R. Kumar, R. Lysecky, F. Vahid, D. M. Tullsen. Application-Specific Customization of Parameterized FPGA Soft-Core Processors. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 261-268, 2006.
7. D. Sheldon, R. Kumar, F. Vahid, D. M. Tullsen, R. Lysecky. Conjoining Soft-Core FPGA Processors. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 694-701, 2006.
8. R. Lysecky, F. Vahid, S. Tan. A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 57-62, 2005.
9. R. Lysecky, F. Vahid. A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. IEEE/ACM Design Automation and Test in Europe Conference (DATE), pp. 18-23, 2005.
10. R. Lysecky, F. Vahid, S. Tan. Dynamic FPGA Routing for Just-in-Time Compilation. IEEE/ACM Design Automation Conference (DAC), pp. 954-959, 2004.
11. R. Lysecky, F. Vahid. A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. IEEE/ACM Design Automation and Test in Europe Conference (DATE), pp. 480-485, 2004.
12. C. Zhang, F. Vahid, R. Lysecky. A Self-Tuning Cache Architecture for Embedded Systems. IEEE/ACM Design Automation and Test in Europe Conference (DATE), pp. 16-20, 2004.
13. R. Lysecky, F. Vahid. A Codesigned On-Chip Logic Minimizer. IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 109-113, 2003.
14. R. Lysecky, F. Vahid. On-Chip Logic Minimization. IEEE/ACM 40th Design Automation Conference (DAC), pp. 334-337 2003.
15. G. Stitt, R. Lysecky, F. Vahid. Dynamic Hardware/Software Partitioning: A First Approach. IEEE/ACM 40th Design Automation Conference (DAC), pp. 250-255, 2003.
16. R. Lysecky, S. Cotterell, F. Vahid. A Fast On-Chip Profiler Memory. IEEE/ACM 39th Design Automation Conference (DAC), pp. 28-33, pp. 28-33, 2002.
17. G. Stitt, F. Vahid, T. Givargis, R. Lysecky. A First-step Towards an Architecture Tuning Methodology for Low Power. IEEE/ACM International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), pp. 187-192, Novemeber 2000.
18. R. Lysecky, F. Vahid, T. Givargis. Experiments with the Peripheral Virtual Component Interface. IEEE/ACM International Symposium on System Synthesis (ISSS), pp. 221-224, September 2000.
19. R. Lysecky, F. Vahid, T. Givargis. 'T'echniques for Reducing Read Latency of Core Bus Wrappers''. IEEE/ACM Design Automation and Test in Europe Conference (DATE), pp. 84-91, March 2000.
    Received Best Paper Award
20. R. Lysecky, F. Vahid, T. Givargis, R. Patel. Pre-fetching for Improved Core Interfacing. IEEE/ACM International Symposium on System Synthesis (ISSS), pp. 51-55, 1999.

Book Chapters

1. R. Lysecky. Hardware Description Languages. Chapter in Digital Design textbook, F. Vahid, John Wiley and Sons, 2006.

Technical Reports

1. J. Villarreal, R. Lysecky, S. Cotterell, F. Vahid. Loop Analysis of Embedded Applications. UC Riverside Technical Report UCR-CSE-01-03, 2001.