Publications

Patents

1. F. Vahid, R. Lysecky, G. Stitt. Warp Processor for Dynamic Hardware/Software Partitioning. US Patent 7,356,672, 2008.

Books

1. F. Vahid, R. Lysecky. VHDL for Digital Design. John Wiley and Sons, 2007.
2. F. Vahid, R. Lysecky. Verilog for Digital Design. John Wiley and Sons, 2007.

Journal Publications

1. R. Lysecky. Scalability and Parallel Execution of Warp Processing - Dynamic Hardware/Software Partitioning. International Journal on Parallel Programming, To Appear.
2. R. Lysecky, F. Vahid. Design and Implementation of a MicroBlaze-based Warp Processor. ACM Transactions on Embedded Computing Systems (TECS), To Appear.
3. F. Vahid, G. Stitt, R. Lysecky. Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. IEEE Computer, Vol. 41, No. 7, pp. 40-46, July 2008.
4. R. Lysecky, G. Stitt, F. Vahid. Warp Processors. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, No. 3, pp. 659 - 681, 2006.
5. C. Zhang, F. Vahid, R. Lysecky. A Self-Tuning Cache Architecture for Embedded Systems. ACM Transactions on Embedded Computing Systems (TECS), Vol. 3, No. 2, pp. 407-425, May 2004.
6. R. Lysecky, S. Cotterell, F. Vahid. A Fast On-Chip Profiler Memory using a Pipelined Binary Tree. IEEE Transaction on Very Large Scale Integration (TVLSI), Vol. 12, No. 1, pp. 120-122, January 2004.
7. F. Vahid, R. Lysecky, C. Zhang, G. Stitt. Highly Configurable Platforms for Embedded Computing Systems. Microelectronics Journal, Vol. 34, No. 11, pp. 1025-1029, 2003.
8. R. Lysecky, F. Vahid. Pre-fetching for Improved Bus Wrapper Performance in Cores. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 7, Number 1, January 2002.

Conference Publications

1. M. Hammerquist, R. Lysecky. Design Space Exploration for Application-Specific FPGAs in System-on-a-Chip Designs. IEEE System on a Chip Conference (SOCC), To Appear, 2008.  Δ  Δ
2. L. Saldanha, R. Lysecky. Hardware/Software Partitioning of Floating Point Software Applications to Fixed-Pointed Coprocessor Circuits. International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), To Appear, 2008. Δ  Δ
3. A. Nair, R. Lysecky. Non-Intrusive Dynamic Application Profiler for Detailed Loop Execution Characterization. International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), To Appear, 2008. Δ  Δ
4. R. Lysecky. Low-Power Warp Processor for Power Efficient High-Performance Embedded Systems. IEEE/ACM Design Automation and Test in Europe Conference (DATE), 2007.
5. D. Sheldon, R. Kumar, R. Lysecky, F. Vahid, D. M. Tullsen. Application-Specific Customization of Parameterized FPGA Soft-Core Processors. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), To Appear, November 2006.
6. D. Sheldon, R. Kumar, F. Vahid, D. M. Tullsen, R. Lysecky. Conjoining Soft-Core FPGA Processors. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2006.
7. R. Lysecky, F. Vahid, S. Tan. A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2005.
8. R. Lysecky, F. Vahid. A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. IEEE/ACM Design Automation and Test in Europe Conference (DATE), March 2005.
9. R. Lysecky, F. Vahid, S. Tan. Dynamic FPGA Routing for Just-in-Time Compilation. IEEE/ACM Design Automation Conference (DAC), June 2004.
10. R. Lysecky, F. Vahid. A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. IEEE/ACM Design Automation and Test in Europe Conference (DATE), February 2004.
11. C. Zhang, F. Vahid, R. Lysecky. A Self-Tuning Cache Architecture for Embedded Systems. IEEE/ACM Design Automation and Test in Europe Conference (DATE), February 2004.
12. R. Lysecky, F. Vahid. A Codesigned On-Chip Logic Minimizer. IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2003.
13. R. Lysecky, F. Vahid. On-Chip Logic Minimization. IEEE/ACM 40th Design Automation Conference (DAC), June 2003.
14. G. Stitt, R. Lysecky, F. Vahid. Dynamic Hardware/Software Partitioning: A First Approach. IEEE/ACM 40th Design Automation Conference (DAC), June 2003.
15. R. Lysecky, S. Cotterell, F. Vahid. A Fast On-Chip Profiler Memory. IEEE/ACM 39th Design Automation Conference (DAC), pp. 28-33, June 2002.
16. G. Stitt, F. Vahid, T. Givargis, R. Lysecky. A First-step Towards an Architecture Tuning Methodology for Low Power. IEEE/ACM International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), pp. 187-192, Novemeber 2000.
17. R. Lysecky, F. Vahid, T. Givargis. Experiments with the Peripheral Virtual Component Interface. IEEE/ACM International Symposium on System Synthesis (ISSS), pp. 221-224, September 2000.
18. R. Lysecky, F. Vahid, T. Givargis. 'T'echniques for Reducing Read Latency of Core Bus Wrappers''. IEEE/ACM Design Automation and Test in Europe Conference (DATE), pp. 84-91, March 2000.
    Received Best Paper Award
19. R. Lysecky, F. Vahid, T. Givargis, R. Patel. Pre-fetching for Improved Core Interfacing. IEEE/ACM International Symposium on System Synthesis (ISSS), pp. 51-55, November 1999.

Book Chapters

1. R. Lysecky. Hardware Description Languages. Chapter in Digital Design textbook, F. Vahid, John Wiley and Sons, 2006.

Technical Reports

1. J. Villarreal, R. Lysecky, S. Cotterell, F. Vahid. Loop Analysis of Embedded Applications. UC Riverside Technical Report UCR-CSE-01-03, 2001.