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An asynchronous, single-chip, high-speed communication adaptive echo canceller
was designed in this project. Adaptation is based on the LMS algorithm
with power-of-two convergence factor. Cancellation is performed by a
128-coefficient
adaptive finite impulse response filter whose coefficients are updated
every cycle. The LMS power-of-two update equations were modified to allow
a pipelined implementation. Pipelining the adaptation and echo estimation
operations enabled hardware minimization, a high sampling rate, and no increase
in convergence time. The resulting circuit updates the filter coefficients and
generates the output at a sampling rate greater than 205 kHz. The chip was
designed using 0.8-micron CMOS standard cells. The single-chip layout requires
a die size of 9.25 mm by 7.25 mm.
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