ECE 274 Digital Logic

ECE 274 Digital Logic - Spring 2007

Course Information

Instructor
     Susan Lysecky, (slysecky@ece.arizona.edu)
     Office Hours: M 1:00-2:00PM, W 10:00-11:00AM, or by appointment.
     Office: ECE 320C

Teaching Assistants
     Tuan Pham, tuanp1@ece.arizona.edu
           Office Hours: W 1-2PM
           Office: Carrel 9
     Haiyong Zhang, hzhang@ece.arizona.edu

Lecture
MWF 12:00-12:50PM, ILC 140

Lab

Section 2 T 800AM – 1050 AM ECE 301 TA: Haiyong Zhang

Section 3 T 200PM – 450 PM ECE 301 TA: Tuan Pham

Section 4 W 200PM – 450 PM ECE 301 TA: Tuan Pham

Section 6 R 1100AM – 150 PM ECE 301 TA: Haiyong Zhang

Section 8 F 200PM – 450 PM ECE 301 TA: Haiyong Zhang

General Course Information
General course information has been moved here.

Lecture Schedule

Lecture schedule subject to change.

W Jan 10 - Course overview pdf

F Jan 12 - Chapter 1: Introduction to Digital Logic Design pdf

M Jan 15 - Martin Luther King Day - NO CLASSES

W Jan 17 - Chapter 2.1-2.4 pdf

F Jan 19 - Chapter 2.9-2.10 pdf

M Jan 22 - Chapter 2.9-2.10 (continued) pdf

W Jan 24 - Chapter 2.5 - 2.6 pdf

F Jan 26 - Chapter 2.7 - 2.8 pdf

M Jan 29 - NO CLASS TODAY

W Jan 31 - Chapter 3.1 - 3.3, Chapter 4.1 pdf

F Feb 2 - NO CLASS TODAY.
M Feb 5 - Finish Chapter 4.1
W Feb 7 - Chaper 4.2 - 4.4 pdf
F Feb 9 - Chaper 4.5 - 4.8 pdf
M Feb 12 - Chaper 4.9 pdf Decimal to Binary Cheat Sheet pdf
W Feb 14 - Chapter 5.1 - 5.2 pdf
W Feb 16 - Chapter 5.3 - 5.4 pdf
M Feb 19 - Midterm Review Session
W Feb 21 - Special Office Hours
F Feb 23 - Midterm 1 (Chapter 1 - 4)
M Feb 26 - Review Midterm 1
W Feb 28 - Finish Fast Adders
Chapter 5.6-5.8 pdf
F Mar 2 - Chapter 6.1 - 6.2 pdf
M Mar 5 - Chapter 6.3 - 6.5, Shifters, Incrementors, ALUs pdf
W Mar 7 - Review Combinational Building Blocks (Chapter 5 & 6)
F Mar 9 - Chapter 7.1 - 7.7 pdf
M Mar 12 - Spring Break
W Mar 14 - Spring Break
F Mar 16 - Spring Break
M Mar 19 - Chapter 7.8 - 7.9 pdf
W Mar 21 - More register examples, finish counter slides.
F Mar 23 - Chapter 8.1 pdf
M Mar 26 - Finish Ch 8.1 (FSM) slides
W Mar 28 - Continue 8.1
F Mar 30 - Chapter 8.2, 8.3 pdf
M Apr 2 - Midterm 2 Review Session
W Apr 4 - Midterm 2
F Apr 6 - NO CLASS TODAY
M Apr 9 - Finish 8.3 (Moore vs. Mealy FSMs)
W Apr 11 - Ch 8.5 - pdf
F Apr 13 - Finish Ch 8.5
M Apr 16 - Review Solutions to Midterm 2
W Apr 18 - TA Office Hours 12-2, Carrel 9
F Apr 20 - NO CLASS TODAY
M Apr 23 - Introduction to RTL Design pdf
W Apr 25 - RTL Design Continued pdf
F Apr 27 - Underlying FPGA Implementation pdf
M Apr 30 - Final Exam Review Session, Lab 5 Reports Due in class
W May 2 - Extended Office Hours (No class, I'll be in my office to answer questions 10-11, 12-1), Last day to update d2l scores
F May 11 - FINAL EXAM 11:00 - 1:00

Homework

Homework 1 - Due at beginning of class Friday Feburary 2, 2007.

Homework 2 - Due at beginning of class Wednesday Feburary 14, 2007.

Homework 3 - Due at beginning of class Friday, March 9, 2007.

Homework 4 - Due at beginning of class Wednesday, March 28, 2007.

Homework 5 - Due at beginning of class Monday, April 23, 2007.

Lab Schedule/Information

Labs must be finished on-time. Late labs will not be accepted.

A lab report, using the specified lab report format, is required for all lab assignments, including tutorials, and is due at the beginning of the following lab period after the lab is due. Individual labs may also require additional information such as schematics, simulations, manually performed tasks, or a summary of results. Please be sure to include this information in your lab report. Your lab demo will count for 80% of each lab score. Your lab report will count for 20% of each lab score.

Students should work in groups of two for laboratory assignments. However, students have the option of working on their own if computing resources permit. You must choose your lab partner during the first lab and inform your TA of your selection. Your lab partner will remain the same for the of the semester. Please choose your lab partner wisely.

Lab schedule subject to change

Description Points

Lab 1 (Starts Week of Jan 22 - Jan 26)
Lab Duration: 2 lab sessions Introduction to Verilog Simulation and Synthesis

Xilinix ISE 8.1 Simulation Tutorial
Xilinx ISE 8.1 Synthesis Tutorial
Xilinx Spartan-3E Starter Kit Board User Guide
50

Lab 2 (Starts Week of Feb 12 - Feb 16)
Lab Duration: 1 lab session Lab 2: Decoder 100

Lab 3 (Starts Week of Feb 26 - Mar 2 )
Lab Duration: 2 lab sessions Lab 3: Subtractors 100

Lab 4 (Starts Week of Mar 26 - 30)
Lab Duration: 2 lab sessions Lab 4 Tutorial: Modeling and Testing Finite State Machines (FSMs)

laser_timer.v
laster_timer_tb.v
Lab 4: 4-Bit Up/Down Counter

counter.v
counter_fsm.v
lcd_display.v
100

Lab 5 (Starts Week of Apr 9 - 13)
Lab Duration: 2 lab sessions Lab 5: 2-bit Multiplier 150

ANNOUNCEMENTS

Section 2	T	800AM – 1050 AM	ECE 301	TA: Haiyong Zhang
Section 3	T	200PM – 450 PM	ECE 301	TA: Tuan Pham
Section 4	W	200PM – 450 PM	ECE 301	TA: Tuan Pham
Section 6	R	1100AM – 150 PM	ECE 301	TA: Haiyong Zhang
Section 8	F	200PM – 450 PM	ECE 301	TA: Haiyong Zhang

	Labs must be finished on-time. Late labs will not be accepted.
	A lab report, using the specified lab report format, is required for all lab assignments, including tutorials, and is due at the beginning of the following lab period after the lab is due. Individual labs may also require additional information such as schematics, simulations, manually performed tasks, or a summary of results. Please be sure to include this information in your lab report. Your lab demo will count for 80% of each lab score. Your lab report will count for 20% of each lab score.
	Students should work in groups of two for laboratory assignments. However, students have the option of working on their own if computing resources permit. You must choose your lab partner during the first lab and inform your TA of your selection. Your lab partner will remain the same for the of the semester. Please choose your lab partner wisely.
	Lab schedule subject to change

	Description	Points
Lab 1 (Starts Week of Jan 22 - Jan 26) Lab Duration: 2 lab sessions	Introduction to Verilog Simulation and Synthesis Xilinix ISE 8.1 Simulation Tutorial Xilinx ISE 8.1 Synthesis Tutorial Xilinx Spartan-3E Starter Kit Board User Guide	50
Lab 2 (Starts Week of Feb 12 - Feb 16) Lab Duration: 1 lab session	Lab 2: Decoder	100
Lab 3 (Starts Week of Feb 26 - Mar 2 ) Lab Duration: 2 lab sessions	Lab 3: Subtractors	100
Lab 4 (Starts Week of Mar 26 - 30) Lab Duration: 2 lab sessions	Lab 4 Tutorial: Modeling and Testing Finite State Machines (FSMs) laser_timer.v laster_timer_tb.v Lab 4: 4-Bit Up/Down Counter counter.v counter_fsm.v lcd_display.v	100
Lab 5 (Starts Week of Apr 9 - 13) Lab Duration: 2 lab sessions	Lab 5: 2-bit Multiplier	150