ECE 474A/574A Computer-Aided Logic Design, Fall 2006

Course Information

     Instructor
       Susan Lysecky, slysecky@ece.arizona.edu
    Office Hours: Monday 1-2p,Thursday 10-11a, or by appointment.
    Office: ECE 320C
 
  Teaching Assistant
    Xiaoyan Wei, xwei@email.arizona.edu
    Office Hours: Wednesday 10-11a, Friday 2-4p.
    Office: ECE 320, Carrel 5
 
  Lecture
    MWF 12:00PM-12:50PM, CHVEZ 111
 
  Textbook
    (Required) Digital Design, Frank Vahid, John Wiley & Sons, ISBN 0470044373
    (Optional) Logic Synthesis and Verification Algorithms, Gary Hachtel and Fabio Somenzi, Springer, ISBN 0387310045
 
  Grading
    Grading will be evaluated on an individual basis. You will not be competing with other students for your grade. If all students do well in the class, everyone will get an A. Your grade is dependent on the effort you put into the class. Letter grades will be assigned as follows: 90% and above is an A, 80% and above is a B, 70% and above is a C, 60% and above is a D, and less than 60% is an E.

    The grading is based on a weighted sum as follows:

     25% Final
     30% Midterms (2 Midterms)
     10% Homework
     20% Programming Assignments
     10% Term Project
     5% Participation

    Students enrolled in ECE 574A will have additional/different homework, lab assignments, and term project requirements.
 
  Syllabus
    Printable version of the syllabus
 
  Policies
    Punctuality: Please arrive on-time to class. If you are late, try not to disrupt others and enter as quietly as possible.

    Cell Phones: Please turn off you cell phone before you come to class.

    Academic Dishonestly: Any academic dishonesty will not be tolerated. Unless otherwise specifically stated by your instructor or teaching assistant, all course work should be done on your own. Please consult the UA Code of Academic Integrity.

Engineering is a social discipline requiring good people skills. Study groups will enable you to get to know others in your field, while enhancing your learning. It is strongly encourged to form study groups and review the course material together. However, you should not work on homework or lab assignment together. If you have questions on these specific problems come see the instructor or TA.

    Reading: Be prepared. Read over the material before class. For the most part lecture will follow mostly the organization of the book. I will do my best to post upcoming lecture topics. Check the class webpage regularly for announcements.

    Regrades: All requests for regrades must be submitted in writting within one week of the distribution of the graded material. Problems requested to be regraded will be regraded in their entirety, which could possibly result in a lower score for the requested problem.

    Late Homeworks: Late homework assignment will be accepted for a maximum of two days after the due date. For each day your assignment is late, 10% of the total possible points will be deducted from your score.

 

Lecture Schedule

  M Aug 21 Class Overivew
     W Aug 23 Start Reviewing Chapters 1-3,
   Chapter 1   pdf  
   Chapter 2.1-2.6   pdf  
     F Aug 25    Finish Verilog Example

 
     M Aug 28    Chapter 2.6-2.10   pdf  
   Start Chapter 3   pdf  
     W Aug 30  
     F Sept 1  

 
     M Sept 4 Labor Day - NO CLASS
     W Sept 6 Verilog Example - look at FSMs
     F Sept 8 Chapter 4.1 - 4.3 pdf

 
     M Sept 11 Finish Ch 4.1-4.3
Ch 6.1-6.3 pdf
     W Sept 13  
     F Sept 15  

 
     M Sept 18  
     W Sept 20 Midterm 1
     F Sept 22 NO CLASS

 
     M Sept 25  
     W Sept 27  
     F Sept 29 Ch 6.4a pdf

 
     M Oct 2 Ch 4.4 - 4.10 pdf
     W Oct 4  
     F Oct 6 Ch 6.4b pdf

 
     M Oct 9 Ch 5.1-5.2 pdf
     W Oct 11  
     F Oct 13 Ch 5.3 pdf

 
     M Oct 16 Ch 5.4 - 5.8 pdf
     W Oct 18  
     F Oct 20  
 
     M Oct 23 NO CLASS - I'll have extended office hours (12-2)
     W Oct 25 Review
     F Oct 27 Midterm 2
 
     M Oct 30 Logic Minimization - Part 1 (Quine-McCluskey)    2 slides/page    1 slide/page
     W Nov 1  
     F Nov 3  
 
     M Nov 6 Talk about Term Projects
Logic Minimization - Part 2 (Espresso)    2 slides/page    1 slide/page
     W Nov 8 Logic Minimization - Part 3 (Branch and bound)    2 slides/page    1 slide/page
     F Nov 10 Logic Minimization - Part 4 (Simulated Annealing and Dynamic Programming)    2 slides/page    1 slide/page
 
     M Nov 13 Veterans Day - NO CLASS
     W Nov 15 Go over programming project 4.
     F Nov 17 Binary Decision Diagrams    2 slides/page    1 slide/page
 
     M Nov 20 Finish BDD slides
     W Nov 22 NO CLASS - Have a nice Thanksgiving!
     F Nov 24 Thanksgiving Recess - NO CLASS
 
     M Nov 27 RTL Optimizations and Tradeoffs    2 slides/page    1 slide/page
     W Nov 29 Scheduling Algorithms    2 slides/page    1 slide/page
     F Dec 1  
 
     M Dec 4 Review
     W Dec 6 NO CLASS, Term Project Due
 
     W Dec 13 Final Exam 11:00AM-1:00PM
 

Homework

  Assignments
  • HW 1, Due September 15, 2006.
  • HW 2, Due October 20, 2006.
  • HW 3, Due November 27, 2006.

Programming Assignments

  Assignments

  Resources