ECE 474A/574A

Susan Lysecky, slysecky@ece.arizona.edu
Office Hours: M 12-1, W 3-4, or by appointment.
Office: ECE 356C (Formerly 320C)

Sai Ranganath Srinivasan
srinivas@ece.arizona.edu

MWF 2:00PM-2:50PM, HARV 305
Course Website: http://www.ece.arizona.edu/~ece474a

There is no mandatory textbook for this course. Lecture material will mainly be derived from the following textbooks.

• (Optional) Digital Design, Frank Vahid, John Wiley & Sons, ISBN 0470044373
  
• (Optional) Logic Synthesis and Verification Algorithms, Gary Hachtel and Fabio Somenzi, Springer, ISBN 0387310045

Other related textbooks

• Synthesis and Optimization of Digital Circuits, Giovanni De Micheli, McGraw-Hill, ISBN 0070163332
  
• Logic Synthesis and Verification , Soha Hassoun and Tsutomu Sasaoor, Springer, ISBN 0792376064
  
• Advanced BDD Optimization , Rüdiger Ebendt, Görschwin Fey, and Rolf Drechsler, Springer, ISBN 0387254536
  
• Principles of Digital Design , Daniel D. Gajski, Prentice Hall, ISBN 0133011445
  
• Fundamental of Digital Logic , Stephen Brown and Zvonko Vranesic, McGraw Hill, ISBN 0072838787
  

Grading will be evaluated on an individual basis. You will not be competing with other students for your grade. If all students do well in the class, everyone will get an A. Your grade is dependent on the effort you put into the class. Letter grades will be assigned as follows: 90% and above is an A, 80% and above is a B, 70% and above is a C, 60% and above is a D, and less than 60% is an E.

The grading is based on a weighted sum as follows:
30% Final
30% Midterms (2 Midterms)
5% Homework
20% Programming Assignments
10% Term Project
5% Participation

Students enrolled in ECE 574A will have additional/different homework, lab assignments, and term project requirements.

Punctuality: Please arrive on-time to class. If you are late, try not to disrupt others and enter as quietly as possible.

Absence: If you miss a homework/project deadline or exam, you need to bring written documentation (i.e. tow truck bill, receipt from doctor's office, court summons, etc.) to verify your whereabouts. You can remove any private information.

Cell Phones: Please turn off you cell phone before you come to class.

Academic Dishonestly: Any academic dishonesty will not be tolerated. Unless otherwise specifically stated by your instructor or teaching assistant, all course work should be done on your own. Please consult the UA Code of Academic Integrity.

Engineering is a social discipline requiring good people skills. Study groups will enable you to get to know others in your field, while enhancing your learning. It is strongly encouraged to form study groups and review the course material together. You may work on homework assignments together. You may NOT work on programming projects or exams together. If you are in doubt, don’t do it!

Reading: Be prepared. Since there is no required textbook, it is difficult to say read over the material before class. I will however do my best to post upcoming lecture topics and the source. Check the class webpage regularly for announcements.

Regrades: All requests for regrades must be submitted in writing within one week of the distribution of the graded material. Problems requested to be regraded will be regraded in their entirety, which could possibly result in a lower score for the requested problem.

Late Homeworks/Projects: Late assignments will be accepted for a maximum of two days after the due date. For each day (doesn't matter if it's a weekend) your assignment is late, 10% of the total possible points will be deducted from your score.

This course is an introduction to Computer-Aided Logic (CAD) Design. This is a highly-active research area, enabling the design of more and more complex digital systems.

In this course we will look at three areas, digital design, optimization techniques, and the use of software tools. We will look at how to specify functionality at a variety of abstractions, use industry-standard tools to simulate these designs, and investigate some of the underlying optimization techniques utilized. Topics include, but are limited to the following

• Design and implementation of sequential circuits
• Register-Transfer Level (RTL) Design
• Optimization and Tradeoffs of combinational and sequential circuits
• Heuristic Minimization of Two-Level Circuits
• Binary Decision Diagrams (BDDs)
• Multi-Level Minimization

In addition to homeworks, students will be expected to implement a variety of Verilog and C/C++ projects throughout the semester, with a final project to be discussed near the end of the semester.