ECE 474A/574A, Fall 2007

Project 1 - Structural vs. Behavioral ALU, Due September 7, 2007 at 8:00 PM.
Project 2 - I²C Bus Interface, Due ~~October 3~~ October 10, 2007 at 8:00 PM.
Project 3 - FSM+D Interface to Memory, October 29, 2007 at 8:00 PM.
Project 4 - 2-Level Logic Minimizer November 30, 2007 at 8:00 PM.

Xilinx WebPACK - Xilinx WebPack project creation and simulation tutorial. (Available in ECE 250, ECE 232, or free to download on your own machine)
Verilog by Example - Verilog tutorial and sample code.
How do I use turnin?