ECE 474A/574A

Susan Lysecky, slysecky@ece.arizona.edu
Office Hours: M 9-10, W 3-4, or by appointment.
Office: ECE 356C

MWF 12:00P-12:50P, ARCH 103
Course Website: http://www.ece.arizona.edu/~ece474a

There is no required textbook for this course. The class notes/slides are sourced from the following materials

• Digital Design, Frank Vahid, John Wiley & Sons, ISBN 0470044373
  
• Verilog for Digital Design, Frank Vahid and Roman Lysecky, John Wiley & Sons, ISBN 9780470052624
• Digital Design, M. Morris Mano and Michael D. Ciletti, Prentice Hall, ISBN 0131989243
• Logic Synthesis and Verification Algorithms, Gary D. Hachtel and Fabio Somenzi, Springer, ISBN 0387310045
• Logic Minimization Algorithms for VLSI Synthesis, Robert K. Brayton, Gary D. Hathtel, C. McMullen, and Alberto L. Sangiovanni-Vincentelli, Kluwer Academic Publishers, ISBN 0898381649
• Introduction to Algorithms, Thomas H. Cormen, Charles E. Leiserson, and Ronald L. Rivest, McGraw-Hill, 0070131430
• Fundamentals of Digital Logic Design with Verilog Design, Stephen Brown and Zvonko Vranesic, McGraw-Hill Higher Education, ISBN 0072838787
• Synthesis and Optimization of Digital Circuits, Giovanni De Micheli, McGraw-Hill, ISBN 0070163332

Grading will be evaluated on an individual basis. You will not be competing with other students for your grade. If all students do well in the class, everyone will get an A. Your grade is dependent on the effort you put into the class. Letter grades will be assigned as follows: 90% and above is an A, 80% and above is a B, 70% and above is a C, 60% and above is a D, and less than 60% is an E.

The grading is based on a weighted sum as follows:
65% Exams (4 Exams, lowest score dropped)
30% Programming Projects (2-3 Projects, not equally weighted)
5% Participation/In-class exercises (ICE)

Students enrolled in ECE 574A will have additional/different exam and programming assignment requirements.

Punctuality: Please arrive on-time to class. If you are late, try not to disrupt others and enter as quietly as possible.

Absence: If you miss a project deadline or exam, you need to bring written documentation (i.e. tow truck bill, receipt from doctor's office, court summons, etc.) to verify your whereabouts. You can remove any private information.

Cell Phones: Please turn off you cell phone before you come to class.

Academic Dishonestly: Any academic dishonesty will not be tolerated. Unless otherwise specifically stated by your instructor or teaching assistant, all course work should be done on your own. Please consult the UA Code of Academic Integrity.

Engineering is a social discipline requiring good people skills. Study groups will enable you to get to know others in your field, while enhancing your learning. It is strongly encouraged to form study groups to work on the practice problems or to review the course material together. You may NOT work on programming projects or exams together. If you are in doubt, don’t do it!

Reading: Be prepared. Read over material before class. I will however do my best to post upcoming lecture topics and the source. Check the class webpage regularly for announcements.

Regrades: All requests for regrades must be submitted in writing within one week of the distribution of the graded material. Assignments requested to be regraded will be regraded in their entirety, which could possibly result in a lower score for the requested problem/assignment.

Late Programming Assignments: No late assignments will be accepted unless you have already made arrangements with the instructor before the due date.

This course is an introduction to Computer-Aided Logic Design. This is a highly-active research area, enabling the design of more and more complex digital systems. In this course we will mainly focus on three areas - specification, optimization, and the use of software tools.

We will look at how to specify functionality at a variety of abstractions, use industry-standard tools to simulate these designs, and investigate some of the underlying optimization techniques utilized.

Topics include, but are not limited to the following

• Design and implementation of sequential circuits
• Register-Transfer Level (RTL) Design
• Optimization and Tradeoffs of combinational and sequential circuits
• Exact and Heuristic Minimization of Two-Level Circuits
• Binary Decision Diagrams (BDDs)

In addition to written problems, students will be expected to implement a variety of Verilog and C/C++ projects throughout the semester.