- Project 1
- Structural vs. Behavioral ALU,
due February 1, 2008 at 8:00 pm.
- Project 2
- FSM + D : Soda Machine,
due February 18, 2008 at 8:00 pm.
-
Project 3
- I2C Bus Interface,
due March 26, 2008 at 8:00 pm.
Parallel Memory Access Files
I2C Bus Interface - Skeletal Files
- Project 4
- 2-Level Logic Minimizer
Phase 1 due April 16, 2008 at 8:00 pm
April 21, 2008 at 8:00 pm
Phase 2 due May 5, 2008 at 8:00 pm.
Test Files
C++ - Skeletal Files
C - Skeletal Files
- Xilinx
WebPACK - Xilinx WebPack project creation and
simulation tutorial.
- Xilinx Software available in ECE 250, ECE 232, or free to
download on your own machine)
- Click on "Download ISE WebPACK for Windows" link
- Download Type - ISE WebPACK, Version - 9.2i, OS - Windows
- Clikc on "WebInstall"
- Login - you will need to register to get an account
Verilog by Example
- Verilog tutorial and sample code.
How do I use turnin?
How do I
transfer files to and from my ECE account?