CE Seminar: Ali Akoglou, "SCARS: Scalable Self-Configurable Architecture for Reusable Space Systems" 29 April, 2:00-3:00 in ECE 530
Coordinates:
| Date: | 29 April, 2:00-3:00 |
| Title: | SCARS: Scalable Self-Configurable Architecture for Reusable Space Systems |
| Speaker: | Ali Akoglou |
| Location: | ECE530 |
Abstract:
Creating an environment of “no doubt” for mission success is critical to most space applications. On-board methods to not only monitor the system’s health, but also reconfigure the system to respond to hardware anomalies automatically with recovery action are essential. With reconfigurable devices such as Field Programmable Gate Arrays (FPGAs), designers are provided with a seductive tool to use as a basis for sophisticated but highly reliable platforms. SCARS project specifically focuses on developing an architecture in which individual, modular components/subsystems: 1) coordinate their actions for broader range of objectives hence go beyond mission-specific requirements; 2) adapt to changes in mission objectives over time and optimize computing and communication capability; 3) respond to hardware/software anomalies automatically with self-healing action.
We propose a two-level self-healing methodology for increasing the probability of success in critical missions. Our system first undertakes healing at node-level. Failing to rectify system at node-level, network-level healing is undertaken. Our objective is to demonstrate the advantages and feasibility of such an architecture based on scenarios that will quantify the benefits. We have designed a system based on Xilinx Virtex-5 FPGAs and Cirronet DM2200 wireless mesh nodes to demonstrate node level healing and autonomous wireless healing capabilities among networked node devices. The prototype reconfigurable architecture demonstrates network's capability for self-configuration and each node's capability for self-testing, fault-recovery/repair and computation optimization in the context of image processing.
Biography:
Ali Akoglu is an Assistant Professor in the Department of Electrical and Computer Engineering at University of Arizona since 2005. He received the B.S. degree in Computer Engineering from Purdue University in 1998 and the Ph.D. degree in Computer Science from Arizona State University in 2005. His research interests lie in the fields of reconfigurable architectures, CAD tools for FPGA design and application specific instruction set processor design. His recent interests include developing high performance floating point arithmetic core for reconfigurable systems, FPGA based built in self testing and self healing and coarse grain reconfigurable architectures tailored to video compression applications.