CE Seminar: Roman Lysecky, "Warp Processing: Autonomous Performance/Power Optimization for Computing Systems", 19 Feb, 2:00-3:00 in ECE 530
Coordinates:
| Date: | 19 Feb 2008, 2:00-3:00 |
| Title: | Warp Processing: Autonomous Performance/Power Optimization for |
Computing Systems
| Speaker: | Roman Lysecky |
| Location: | ECE530 |
Abstract:
Field-programmable gate arrays (FPGAs) are increasingly becoming an economically viable complement to traditional software-based solutions. FPGAs can implement any hardware circuit simply by downloading bits for the hardware circuit, much in the same way that microprocessors can execute any software program by downloading a new application binary. Implementing a critical region of a software application within an FPGA – a process commonly called hardware/software partitioning – can typically result in substantial overall speedups of 10X-100X over software only implementations. While hardware/software partitioning offers the potential for tremendous speedups, automated partitioning compilers require a significant departure from mainstream software tools and disrupt the well-established relationship between processors, compilers, and applications supported by the concept of a standard software binary. In this talk, we will provide an overview of a new processing technology – called warp processing – that autonomously translates, or recompiles, the kernels on an executing software application as hardware implemented within an on-chip FPGA. The key to this technology is that of hiding the FPGA from software developers, thereby providing designers with the ability to program using any high level language and utilize their existing software development environment. Warp processing is able to provide significant increases in performance and/or reductions in power consumptions by utilizing the underlying FPGA without requiring any designer effort beyond software development.
Biography:
Roman Lysecky is an Assistant Professor of Electrical and Computer Engineering at the University of Arizona. He received his B.S., M.S., and Ph.D. in Computer Science from the University of California, Riverside in 1999, 2000, and 2005, respectively. His primary research interests focus on embedded systems design, with emphasis on dynamic adaptability, hardware/software partitioning, field-programmable gates arrays (FPGAs), and low-power methodologies. He received the Outstanding Ph.D. Dissertation Award from the European Design and Automation Association (EDAA) in 2006 for new directions in embedded system design and embedded software and received the Best Paper Award at the Design Automation and Test in Europe Conference (DATE). He has coauthored two textbooks on hardware description languages, entitled “VHDL for Digital Design” and “Verilog for Digital Design”, published dozens of research papers in top journals and conferences, and holds one US patent.