// Module inverter
// Author  : Srinivasan Ramasubramanian
// Function: Inverts 4 binary inputs: x0 through x3.
// Output  : x0comp through x3comp -- the inverted inputs.
//         : b2, b1, b0  -- three bits that encodes the # of 1s in the input.

module inverter4bit(x0, x1, x2, x3, x0comp, x1comp, x2comp, x3comp, b0, b1, b2);
input x0, x1, x2, x3;
output x0comp, x1comp, x2comp, x3comp;
output b0, b1, b2;

wire m0, m1, m2, m3, m4;
wire c01, c02, c03;
wire c11, c12, c13;
wire c21, c22, c23;
wire c31, c32, c33;
wire c41, c42, c43;
wire v0, v1, v2, v3, v4;
wire b0, b1, b2, b0comp, b1comp, b2comp;


assign m1 = x0 | x1 | x2 | x3;

assign m2 = (x0 & x1) | (x0 & x2) | (x0 & x3) |  
                        (x1 & x2) | (x1 & x3) | 
                                    (x2 & x3) ; 
                                       

// Use the same terms from m2; but use the missing terms
// that way it's easy to see that the combinations are correct.
assign m3 =  (x1 & x2 & x3) | (x0 & x2 & x3) | (x0 & x1 & x3) |
             (x0 & x1 & x2) ;


assign m4 =  (x0 & x1 & x2 & x3);


// Computing bis ->  The bits in the encoded binary value for the # of 1s
// If you use only three inputs, then we need only b2 and b1.
// In this case, b2 and b1 correspond to R and S used in the solution
// by Hadar.

assign b2 = m4; 

assign b2comp = ~b2;

assign b1 = (b2comp & m2);  
//  (b2 & m6) --m6 is obviously 0 as we have only 5 inputs

assign b1comp = ~b1;

assign b0 = (b2comp & b1 & m3) | (b2comp & b1comp & m1);  
// m5 and m7 are zeros. 

assign b0comp = ~b0;



// Computing Vi - indicating if there are i ones or not.

assign v0 = b2comp & b1comp & b0comp; 
assign v1 = b2comp & b1comp & b0;
assign v2 = b2comp & b1 & b0comp;
assign v3 = b2comp & b1 & b0; 
assign v4 = b2 & b1comp & b0comp; // not used in computation of complements.




// Computing C0s and x0comp;
// without using x0, find all combinations.
assign c01 = x1 | x2 | x3;
assign c02 = (x1 & x2) | (x1 & x3) | (x2 & x3);
assign c03 = (x1 & x2 & x3);

assign x0comp = v0 | (v1 & c01) | (v2 & c02) | (v3 & c03);



// Computing C1s and x1comp
assign c11 = x2 | x3 | x0;
assign c12 = (x2 & x3) | (x2 & x0) | (x3 & x0) ;
assign c13 = (x2 & x3 & x0);

assign x1comp = v0 | (v1 & c11) | (v2 & c12) | (v3 & c13);



// Computing C2s and x2comp
assign c21 = x3 | x0 | x1;
assign c22 = (x3 & x0) | (x3 & x1) | (x0 & x1) ;
assign c23 = (x3 & x0 & x1);


assign x2comp = v0 | (v1 & c21) | (v2 & c22) | (v3 & c23);



// Computing C3s and x3comp
assign c31 = x0 | x1 | x2;
assign c32 = (x0 & x1) | (x0 & x2) | (x1 & x2) ;
assign c33 = (x0 & x1 & x2);

assign x3comp = v0 | (v1 & c31) | (v2 & c32) | (v3 & c33);


endmodule